1) Field of the Invention
The present invention relates to a charge pump power supply circuit that generates voltage by charging and discharging a capacitor.
2) Description of the Related Art
A booster circuit and an inverter circuit are used in charge pump power supply circuits. The booster circuit boosts up an input voltage and the inverting circuit inverts the boosted voltage and outputs the inverted voltage. Generally, MOS (metal-oxide semiconductor) transistors are used as switches in a charging-discharging circuit in the charge pump power supply circuits.
FIG. 9 is circuit diagram of a basic structure of the charge pump power supply circuit (booster circuit). As shown in FIG. 9, in a charging circuit, a source electrode of a PMOS (p-channel metal-oxide semiconductor) transistor Q1 is connected to an input power supply Vin, and a drain electrode of the PMOS transistor Q1 is connected to one of the electrodes of a flying capacitor C1. A drain electrode of an NMOS (n-channel metal-oxide semiconductor) transistor Q2 is connected to the other electrode of the flying capacitor C1, and a source electrode of the NMOS transistor Q2 is grounded. Further, a charge-control signal TC that is generated by a control circuit 30 is applied directly to a gate electrode of the NMOS transistor Q2 and applied to a gate electrode of the PMOS transistor Q1 via an inverter Q5.
Moreover, in a discharging circuit, a source electrode of an NMOS transistor Q3 is connected to the input power supply Vin, and a drain electrode of the NMOS transistor Q3 is connected to the other electrode of the flying capacitor C1. A source electrode of a PMOS transistor Q4 is connected to the one of the electrodes and an output capacitor C2 is disposed between a drain electrode of the PMOS transistor Q4 and a ground. Further, a discharge-control signal TD that is generated by the control circuit 30 is applied directly to a gate electrode of the NMOS transistor Q3 and applied to a gate electrode of the PMOS transistor Q4 via an inverter Q6.
FIG. 10 is a time chart of the operations of the charge pump power supply circuit. The charge-control signal TC and the discharge-control signal TD that are generated by the control circuit 30 are control signals that regulate a charge cycle. The charge-control signal TC and the discharge-control signal TD are signals of a binary level that repeat a high-level period and a low-level period alternately, while the polarities differ with the same duty ratio. Therefore, during a period when the level of the charge-control signal TC is high and the level of the discharge-control signal TD is low, each of the PMOS transistor Q1 and the NMOS transistor Q2 performs an ON operation. Moreover, during a period when the level of the discharge-control signal TD is high and the level of the charge-control signal TC is low, each of the NMOS transistor Q3 and the PMOS transistor Q4 perform an ON operation.
In other words, during the period when the level of the charge-control signal TC is high and the level of the discharge-control signal TD is low, the PMOS transistor Q1 that is disposed in series between the input power supply Vin and the ground, and the PMOS transistor Q1 and the NMOS transistor Q2 in a series circuit of the flying capacitor C1 and the NMOS transistor Q2, perform an ON operation. As a result, a charging current I1 flows and a charging operation for the flying capacitor C1 is performed.
Moreover, during the period when the level of the discharge-control signal TD is high and the level of the charge-control signal TC is low, the NMOS transistor Q3 that is disposed between the input power supply Vin and the ground, and the NMOS transistor Q3 and the PMOS transistor Q4 in series circuit of the flying capacitor C1, the PMOS transistor Q4, and the output capacitor C2, perform ON operation. As a result, a discharging current 12 flows and a discharging operation (boosting operation) in which a voltage that is obtained by adding a voltage of the input power supply Vin to a charging voltage of the flying capacitor C1 is transferred to the output capacitor C2, is performed.
By performing the charging operation and the discharging operation alternately, a voltage Vout is obtained in which the voltage of the input power supply Vin is boosted in the output capacitor C2. In that case, an electric charge is stored in the flying capacitor C1 and to reduce a loss while transferring the electric charge stored in the flying capacitor C1 to the output capacitor C2, four MOS transistors that are switches, which have a small ON-state resistance, are used. As a result, with no electric charge or a small amount of electric charge stored in the flying capacitor C1 and the output capacitor C2, as shown in FIG. 10, high rush currents 33 and 34 flow at a time of start up. If the operation is repeated under these conditions, there is a negative effect on the input power supply Vin. Similar problem occurs even in a discharging circuit of an inverting circuit (not shown) of the charge pump power supply circuit.
Various measures have been proposed so far to prevent the rush current. For example, according to Japanese Patent Application Laid-open Publication No. 2003-18822, a constant-current circuit is provided between an input power supply and an output capacitance. At a start up of the power supply, an operation of a charge pump circuit is stopped and charging up to a voltage of output capacitance is performed by the constant-current circuit. Then, a normal operation of the charge pump is started. A technology of shortening a charge cycle at the start up has been disclosed.
Moreover, according to Japanese Patent Application Laid-open Publication No. 2003-219634, a technology in which when the charge pump circuit is not in operation, the flying capacitor C1 and the output capacitor C2 are charged by a back-up charging circuit, is disclosed. According to this technology, further, at a start up of an operation of the charge pump circuit, it is changed to a small-capacity switch that is provided in parallel with a main charge pump switch.
The method disclosed in the Japanese Patent Application Laid-open Publication No. 2003-18822 can reduce the rush current; however, because the voltage of the output capacitor becomes double the input voltage, the rush current flows for charging the output capacitor up to twice the input voltage.
Moreover, according to the technology disclosed in the Japanese Patent Application Laid-open Publication No. 2003-219634, in addition to a necessity of providing a new auxiliary switch, the rush current is generated due to a difference in ON-state resistances of the auxiliary switch and the main switch.